ATSAM4C32 32-bit microcontroller Microchip Technology
ATSAM4C32 32-bit microcontroller Microchip Technology
Microchip Technology ATSAM4C 32-bit microcontroller (MCU) is a system-on-chip for smart energy applications, based on two high-performance Arm® Cortex®-M4 RISC processors. ATSAM4C32 has a maximum operating speed of 120MHz, 2MB embedded flash memory, 304KB SRAM, and an on-chip cache for each core. The dual Arm Cortex-M4 architecture supports the integration of application layer and communication layer functions in a single device, and can expand program and data memory through a 16-bit external bus interface.
A TSAM4C32 MCU's peripheral set includes an advanced encryption engine, tamper-proof, floating-point unit (FPU), a USB full-speed host/device port, five USARTs, two UARTs, two TWIs, and up to seven SPIs. The device also includes a PWM timer, two 3-channel general-purpose 16-bit timers, a low-power calibration RTC running in the backup domain and consumes as low as 0.5µA, and a 50x6 segmented LCD controller.
The SAM4C series is a scalable platform that, together with Microchip's industry-leading SAM4 standard microcontroller, provides smart meter designers with cost structure, performance and flexibility.
1 Features
Application/Master Device Core
ARM Cortex-M4, operating frequency up to 120MHz
Memory Protection Unit (MPU)
DSP instructions
Thumb®-2 instruction set
Command and data cache controller with 2KB cache
2 memory
Up to 2MB embedded flash memory for program code (I-Code bus) and program data (D-Code bus), built-in ECC (2-bit error detection and 1-bit correction per 128 bits)
Up to 256Kb of embedded SRAM (SRAM0) for program data (system bus)
8Kb ROM with embedded bootloader routines (UART) and in-application programming 3 (IAP) routines
Coprocessor (with the ability to separate application, communication or metering functions)
ARM Cortex-M4, operating frequency up to 120MHz
Single-precision floating-point unit (FPU) compliant with IEEE® 754 standard
4DSP instructions
Thumb-2 instruction set
Command and data cache controller with 2Kb cache
5 memory
Up to 32Kb embedded SRAM (SRAM1) for program code (I-Code bus) and program data (D-Code bus and system bus)
Up to 16KB embedded SRAM (SRAM2) for program data (system bus)
Symmetric/asynchronous dual-core architecture
Inter-processor communication based on interrupt
Asynchronous clock
One interrupt controller (NVIC) per core
Each peripheral IRQ is routed to each NVIC input
Shared system controller
6 power supply
Embedded core and LCD regulator for single-supply operation
Power-on reset (POR), brown-out detector (BOD) and dual watchdogs for safe operation
Ultra-low power backup mode (typical value <5µA at 25°C)
7 clock
3MHz to 20MHz oscillator, supports crystal, ceramic resonator or external clock, and also supports clock failure detection
Ultra-low power consumption 768kHz oscillator, support crystal or external clock signal and frequency monitoring
High-precision 4/8/12MHz factory fine-tuning internal RC oscillator with dynamic fine-tuning function
A high-frequency PLL up to 240MHz, an 8MHz PLL with an internal 32kHz input, used as the source of the high-frequency PLL
Low power consumption slows down the clock Internal RC oscillator as a permanent clock
Ultra-low power RTC with Gregorian and Persian calendars, waveform generation in backup mode, and clock calibration circuit for 768kHz crystal frequency compensation circuit
Up to 23 peripheral DMA (PDC) channels
8 encryption
High-performance AES, 128 to 256 bits, with various modes (GCM, CBC, ECB, CFB, CBC-MAC)
TRNG (up to 38Mb/s flow, tested by Diehard and FIPS)
Public key encryption accelerator and related ROM library for RSA, ECC, DSA, ECDSA
Based on secure hash algorithm (SHA1, SHA224, SHA256), DMA-assisted integrity check module (ICM)
