Processor Technology Further Unlocks Supercomputing Performance
Processor Technology Further Unlocks Supercomputing Performance
The ever-increasing complexity and workload diversity of computing jobs requires enormous processing power. Whether used in cloud computing data centers or on-premises applications, the new generation of processors can increase throughput and reduce latency. However, the development of processors requires the development of power supplies. As a result, power supplies often limit the ability to obtain maximum processor performance.
Strong demand for data centers
The recent outbreak has seen a surge in online shopping, streaming and working from home, and hyperscale service and retail providers have expanded their capacity. But to get a fuller picture of data center growth, it should be placed in the context of several other drivers. The major technology driving trends that have emerged over the past 10 years include the Internet of Things (IoT), artificial intelligence (AI), machine learning (ML) at the edge, and exponential growth in operational technology (OT) workloads. Improvements in the performance of industrial operations, such as Industry 4.0, have led to a dramatic increase in OT deployments. These factors require higher computing power, but they also result in more diverse and demanding workloads.
There is an increasing need for data centers to provide flexible, scalable computing infrastructure capable of supporting highly dynamic workloads, enabling cloud computing services or on-premises services. The properties of some computing tasks required by recent trends include low latency, spike neural network algorithms, and search acceleration. Highly optimized specialized processing devices such as Field Programmable Gate Arrays (FPGAs), Graphics Processing Units (GPUs), and Neural Processing Units (NPUs), once rarely used in data centers, have become very common. In addition, a new generation of application-specific integrated circuits (ASICs), such as cluster AI neural network inference engines, are also required to complete high-performance computing tasks.
Advances in processor technology have helped high-performance computing push the boundaries of task throughput, providing flexibility to accommodate greater workload diversity. However, the gains of the technology often depend on other aspects of the system that evolve in parallel.
Technology Trends Improve Computing Performance
Exacerbating Thermal Challenges
In the semiconductor industry, change is inevitable. A new, smaller silicon chip process node goes into production, and the next iteration isn't far off. Smaller geometries allow more individual semiconductor gates to be constructed in a given space. While the 65nm and 55nm process nodes are still the same as usual, mainly used in many integrated circuits (ICs), high performance computing devices such as ASICs, FPGAs, GPUs and NPUs are generally based on process nodes below 12nm, so the 7nm and 5nm process nodes are increasingly more popular. Customers are already lining up to purchase advanced high-performance processors using the 3nm process node.
Increasing the density of individual gates by shrinking the size of them highlights the constraints of managing the thermal characteristics of new processors. When reducing the gate operating voltage, a process called voltage scaling helps reduce heat dissipation per transistor, but thermal management of the entire package remains critical.
A high-performance processor will generally run at its maximum clock rate until thermal constraints require it to be throttled back. Voltage scaling shows that the core voltage of the most complex 5nm process node device drops to 0.75V, and the core voltage of the 3nm process node is expected to drop further to 0.23V. To compound the power challenge, many devices require multiple different voltages and carefully sequenced to avoid permanent damage.
Leading-edge GPUs typically have hundreds of billions of transistors, so current requirements have become large, reaching hundreds of amps. The need for 1000A is not uncommon for clustered AI processors. The current trend is for processors to double their power consumption every two years (Figure 1).
Another aspect of powering such a power-hungry device is that its workload can change within a microsecond, which can create huge transients throughout the power delivery network (PDN).
In large computing systems, power supply and power efficiency have become the most concerned issues. With the advent of ASICs and GPUs that handle complex AI functions, processor power consumption across the industry has increased dramatically. Rack power consumption increases as AI performance is used for large-scale learning and inference application deployments. In most cases, power supply is now the limiting factor in computing performance due to the increasing amount of current that new CPUs need to draw. Powering is not just about power distribution, but also about efficiency, scale, cost, and thermal performance.
power challenge
We have highlighted that advances in semiconductor process technology have created several challenging conditions for PDN. But not all of them are technical. For example, the physical size of these leading edge processing devices will take up a significant proportion of the available board space. Complicating matters, board space is often limited by industry standard form factors.
As board size constraints intensify, the nature of high-performance computing devices requires the support of a variety of ICs, such as memory and optical transceivers, placed close to the processor. In addition, this approach is also suitable for point-of-load (PoL) power regulators due to the dramatic increase in current consumption and the reduction in core voltage. The effects of high-current PCB routing circuits can create I2R losses, clearly discernible voltage drops can have an impact on processor performance, or worse: erratic behavior. In addition, PoL regulators also require high power efficiency to further prevent thermal management complications (Figure 2).
VPD further eliminates power distribution losses and consumption of VR PCB board area. The VPD is similar in design to the Vicor LPD solution, with the added integration of bypass capacitors in the current multiplier or GCM module.
Limited board space combined with the need to mount the voltage regulator close to the processor has led to a new and innovative approach to architecting network PDNs.
powering the processor
PDN becomes the limiting factor
As processor technology continues to evolve, architecting an efficient PDN presents three important, interrelated challenges for power systems engineers.
increase current density
Leading high-performance processors can draw hundreds of amps. Providing sufficient power capacity for the processor involves not only the physical constraints of where to place the point-of-load converters, but also the complex decisions of the PCB routing that directs power from the edge connectors to the converters. High voltage transients caused by extremely dynamic workloads can disrupt other system components.
Improve efficacy
There are two factors that affect power efficiency: I2R losses and conversion efficiency. PCB paths are ideal for low-voltage signal and digital logic trace connections, but for high currents, no matter how short, they can represent significant resistive losses. These I2R losses reduce the voltage supplied to the processor and cause localized heating. With hundreds of other components on the processor card, the size of the power traces is limited, so placing the converter as close to the processor as possible is the only viable alternative.
The efficacy of a converter is a property of its design. Developing high-efficiency PoL converters is a specialized skill that involves an iterative approach to understanding losses in every component, from passives to semiconductors. We've highlighted before that losses are the heat that needs to be dissipated. PoL converter module designers apply their design expertise and expertise to optimize the module's internal design for isothermal packaging.
Keep the PDN simple
Faced with the challenges of PDN, some power architects may choose to create a discrete PoL converter for the processor in order to carefully customize the PDN. However, while this may be a viable solution, it actually adds complexity. A discrete design increases the bill of materials (BOM), creating the need to procure more components and the associated logistical and supply chain costs. Additionally, this approach requires more engineering effort, increases non-recoverable expenditures (NRE), and extends development and testing time. Instead, the modular approach is carefully designed to optimize power for high-performance processors. Well-cooled, integrated power modules can significantly simplify power design, reducing BOM, increasing modification flexibility, and facilitating development. Power modules are compact, power-dense and easily scalable.
A Structured Approach to the Challenges of Powering HPC
To address today's common PDN challenges, Vicor offers two options that match today's most common scenarios.
48V to PoL supply
48V to point of load. Vicor's Power-on-Package (PoP) solution reduces motherboard resistance by 1/50 and processing power pins by 1/10. Utilizing a Factorized Power Architecture (FPA), Vicor minimizes "last inch" resistance with two patented solutions, Lateral Power Delivery (LPD) and Vertical Power Delivery (VPD). These two solutions help processors achieve previously unattainable performance, supporting today's exponentially growing HPC processing demands.
The demand for data centers, edge computing, and the Internet of Things has not abated. The processing speed required for big data is unprecedented. The current maximum processing speed will be too slow in 9 months and power supply will be the focus again. Finding new ways to increase throughput and reduce latency is a long-term challenge. Identifying a highly flexible and scalable solution is the final step in the puzzle. This will minimize the number of redesigns and simplify future modifications. The modular approach accommodates all aspects of current and future high-performance computing.
