Microchip ZL30256 Jitter Attenuator

Microchip ZL30256 Jitter Attenuator
Microchip ZL30256 Jitter Attenuator is a multichannel high-performance, any-rate multiplier and jitter attenuator. The device supports ultra-low jitter clock generation or attenuation from a clock signal while simultaneously generating other independent frequency families, simplifying board design. The device has 3 independent jitter attenuating DPLL channels to create 5 different frequency families. The device has best-in-class jitter performance to create complete clock trees. This feature of the ZL30256 improves design reliability, reduces bill-of-materials cost, and simplifies design by replacing multiple PLLs and external timing components.
characteristic
Up to 3 independent DPLL channels
Excellent jitter performance of 180fs RMS in the 12kHz to 20MHz frequency band to meet the jitter requirements of 10G/40G and 100G PHY
Two Programmable Ultra-Low Jitter Synthesizers Generate Any Frequency Between 1Hz and 1045MHz
A programmable general-purpose synthesizer can generate any clock frequency from 1Hz to 180MHz
8 differential or 16 single-ended (CMOS) ultra-low jitter outputs and two general-purpose CMOS outputs
Accepts up to 10 LVPECL/LVDS/HCSL/LVCMOS inputs
Any input reference can be fed by clock, sync, clock/sync pair, or clock modulated by sync pulses (embedded PPS ePPS and embedded PP2S ePP2S)
Up to four programmable digital PLL/NCOs with loop bandwidths from 14Hz to 470Hz, synchronizable to any clock rate from 1kHz to 900MHz, and synchronized to clock and sync pulses
Automatic uninterrupted reference switching and digital hold when the reference fails, the initial hold accuracy is better than 1ppb (with post-hold filter)
Easy configuration and dynamic programming via SPI/I2C interface
Powered by a single crystal resonator or clock oscillator