FPGA basics

FPGA basics:
1. Basic principles of hardware design
FPGA (Field Programmable Gate Array), namely field programmable gate array, is a product of further development on the basis of programmable devices such as PAL, GAL, CPLD, etc. As a semi customized circuit in the field of ASIC, it not only solves the shortage of customized circuit, but also overcomes the limitation of the number of original programmable device gate circuits.
Speed and area balance and exchange principle:
If the timing margin of a design is large, the frequency of running is far higher than the design requirements, and the chip area consumed by the entire design can be reduced through module reuse, which is the saving of replacing area with speed advantage;
On the contrary, if the timing requirements of a design are very high, and the common method cannot reach the design frequency, then multiple operation modules can be copied in parallel through serial parallel conversion of data streams, the entire design is processed using the ideas of "ping-pong operation" and "serial parallel conversion", and then the data is "parallel serial conversion" at the chip output module. Thus, the area duplication can be used to improve the speed.
Hardware principle: understand the essence of HDL.
System principle: overall grasp.
Synchronous design principle: the basic principle of design timing stability.
2. As an HDL language, Verilog models system behavior hierarchically
The more important levels are system level, algorithm level, register transfer level, logic level, gate level and circuit switch level.
3. In actual work, except for the use of the for loop statement when describing simulation test incentives, the for loop is rarely used in RTL level coding
This is because the for loop will be expanded by the synthesizer into execution statements for all variables. Each variable occupies register resources independently, and cannot effectively reuse hardware logic resources, resulting in huge waste. Generally, case statements are used instead.
4. There is a big difference between if... else... and case in nested description
If... else... has priority. Generally speaking, the first if has the highest priority and the last else has the lowest priority. The case statement is a parallel statement, which has no priority. However, establishing a priority structure requires a lot of logical resources, so if... else... statements should not be used where case can be used.
Supplement: 1. You can also use if; if…;  if…; Describes "parallel" statements without priority.
5. FPGA generally has rich trigger resources, while CPLD combination logic resources are more abundant
6. Composition of FPGA and CPLD
FPGA basically consists of six parts: programmable I/O unit, basic programmable logic unit, embedded block RAM, rich cabling resources, underlying embedded functional unit and embedded special hard core.
The structure of CPLD is relatively simple, mainly composed of programmable I/O unit, basic logical unit, cabling pool and other auxiliary functional modules.