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How far has advanced packaging progressed?

Post Date：2021-09-21，t-Global Technology

In the market for advanced packaging, OSAT companies, foundries, IDM, Fabless companies, EDA tool manufacturers, etc. have all joined them, and they have spent huge amounts of money. The understanding of the concept of "advanced packaging" by these different types of companies and the resulting technology/product layouts are quite different, which can be roughly divided into two categories:

1 It is represented by OSAT, foundry, and IDM. Among them, OSAT develops a flexible multi-product portfolio based on substrates or bumps, and promotes the continuous evolution of the line width/line spacing of the subsequent wafer process; wafers The advantage of foundries and IDMs is that they can provide a complete design and wafer process to adapt to advanced packaging. The second category is Fabless and EDA companies, both of which are related to package design. The advantage of EDA tool vendors is to provide a more complete design process and design tools to facilitate Fabless companies to complete product design faster and shorten the time to market.

However, despite the different paths, their goals for advanced packaging are the same, all pursuing smaller size, smaller line width, and line spacing to provide excellent heat dissipation performance for high-performance products.

At present, the main investment in this round of "advanced packaging" has been invested in wafer foundries and OSAT companies, which are intended to solve process equipment and process problems. Both parties have the advantages of previous investment equipment. The difference lies in wafer foundries. Moving forward from high-precision, OSAT companies are making breakthroughs towards higher integration. Whoever can complete the integration of resources first can gain market advantage.

Changdian Technology
The XDFOI series is a solution launched by Changjiang Electronics Technology Co., Ltd. for Chiplet heterogeneous integration applications, including 2D/2.5D /3D chiplets, etc., which can flexibly realize heterogeneous integration. Compared with the 2.5D TSV package, it has a more flexible design architecture, lower cost, more optimized cost performance, and better reliability. It is suitable for high-end products such as FPGA/CPU/GPU/AI/5G network chips. , Mass production projects and solutions will be available in 2022/2023.

In addition, affected by the expensive cost and yield of TSV, Changjiang Electronics Technology has also introduced a through-silicon-via fan-out wafer-level high-density packaging technology, using Stacked VIA instead of TSV. This technology can realize multi-layer RDL rewiring layers, 2/2um line width pitch, 40um-level narrow bump interconnection, multi-layer chip stacking, integrated high-bandwidth storage, and integrated passive components. In the future, it can also achieve 1/1um high-density line spacing and 20um extremely narrow bump interconnection.

TSMC
TSMC, which has been deeply involved in the packaging field for 10 years, mainly started with large-size high-performance wafer-level packaging 2.5D CoWoS, with a heterogeneous integration area of more than 2400mm2, and its functions include logic circuits, radio frequency circuits and finished memory products. In the next 5-10 years, TSMC’s advanced packaging technology evolution will be more focused on 3DFabric.

3DFabric includes front-end TSMC-SoIC (System Integration Chip), and back-end CoWoS (Chip Last) and InFo (Chip First) series packaging technologies, allowing high-density interconnect chips to be integrated into a package module, thereby increasing bandwidth and reducing latency And increase power efficiency. Customers can focus their logic design on advanced semiconductor technology, and reuse past modules, such as analog, IO, RF, etc., on more mature and lower-cost semiconductor technologies.

In other words, the development of integrated circuits in the past has continued to improve the size and performance of SoCs by adding transistors and multiple device combinations into SoCs. In the future 3D solutions, SoC-SoC 3D integration will be formed based on SoC, and the previous process of substrate or wire connection will be evolved to the use of wafer-level back-end metal connections, and the connection density and performance will be improved.

Intel
Intel’s advanced packaging technology roadmap covers three dimensions: power efficiency, interconnect density, and scalability.

-Multi-block heterogeneous integration improves power efficiency: The heterogeneous integration of individual IPs can bring a larger number of smaller blocks, which can be reused in large quantities, and the development time ranges from 3-4 years for monolithic integrated SoC to multi-chip 2 -3 years is shortened to 1 year, and the chip defect rate is further reduced. In this way, it is convenient to customize products according to the unique needs of customers and meet the needs of products to market quickly.

-Interconnection density: The current Foveros technology can achieve a bump pitch of 50 microns, which will result in approximately 400 bumps per square millimeter. In the future, Intel hopes to reduce the bump pitch to about 10 microns, so that the number of bumps can reach 10,000 per square millimeter. In this way, a smaller and simpler circuit, lower capacitance and power consumption can be realized without fan-in and fan-out.

-Scalability: In this dimension, ODI and CO-EMIB are two key technologies. Intel’s key basic technologies for high-density MCP include EMIB (embedded multi-chip interconnect bridging) 2D packaging, Foveros 3D packaging and 2D/3D fusion Co-EMIB; ODI is Intel’s new all-round interconnection technology, top chip It can communicate horizontally with other small chips like EMIB technology, and it can also communicate vertically with the bottom die through through-silicon vias (TSV) like Foveros technology.

Cadence
Cadence began to develop tools for advanced IC packaging in the early 1990s, ranging from On-the-fly library and Connectivity development to Automatic Wire Bonding and Chip Stacking ( Chip-Stacking), then to the Assembly Design Kit (ADK), and support for parallel collaborative design and collaborative analysis of multiple different IC layouts, all of which help users increase productivity when designing leading multi-chip packages.

TI
Since Jack Kilby invented the integrated circuit, TI has been at the forefront of providing packaging solutions. From the first automatic wire bonding machine and the very early transfer molding process, to MicroSiP and HotRod packaging, copper wire bonding technology, and the pioneering semiconductor miniaturization process, semiconductors are more economical. In the future, TI will continue to apply its packaging innovations to automotive, industrial and personal consumer electronics applications to help users develop smaller and more integrated chips.